1. Field of the Invention
The present invention relates to a method of producing a load for calculating a delay time of a logic circuit, which is composed of P-channel metal oxide semiconductor (PMOS) transistors and N-channel metal oxide semiconductor (NMOS) transistors. The present invention also relates to a recording medium for recording the producing method.
2. Description of Related Art
A group of FIG. 5, FIG. 6 and FIG. 7 shows a processing flow in a conventional method of producing a load for a delay time calculation. FIG. 5 shows the extraction of conventional connection information of circuits in which an NAND 101 and an NAND 102 denoting logic circuits are connected with each other through a wire 103. As shown in FIG. 6, information of the circuit configuration, in which a load is indicated by using resistive-capacitive (RC) elements, is prepared from.the connection information. Here, a source model of the NAND 101 having two inputs is indicated by an electric power source 104 and a resistor 105. Also, a load constituent element 108 is formed by determining to a third-order a parasitic capacitance Cd of an output pin Y of the NAND 101, a resistor-capacitor (RC) distribution constant circuit 107 of the wire 103 and a capacitance Cg of an input pin of the NAND 102 so as to match an admittance which is seen from a gate output terminal of the source model 106.
Thereafter, as shown in FIG. 7, in the load constituent element 108, a composite capacitance of both an input side capacitance of the RC distribution constant circuit 107 and the parasitic capacitance Cd of the output pin Y is indicated by a capacitance C2, a composite capacitance of both an output side capacitance of the RC distribution constant circuit 107 and the capacitance Cg of the input pin is indicated by a capacitance C1, and a load model 109 is prepared by using the capacitances C1 and C2 and a resistance R of the RC distribution constant circuit 107. An approximation to the resistor R and capacitors of the capacitances C1 and C2, which compose the load model 109, is performed by using finite RC elements. Here, even though any type of source model 106 is connected with the load model 109 to form a circuit network shown in FIG. 6, a xcfx80 type model composed of two capacitor elements and one resistor element is formed as the load model 109 so as to approximate a calculated voltage waveform, which is obtained in the gate output terminal of the source model 106 by analyzing the load model 9 shown in FIG. 7, to an actual voltage waveform which is obtained in the gate output terminal of the source model 106 by connecting the load constituent element 108 shown in FIG. 6 with the source model 106.
This approximation method is described in detail, as a prior art, in the literature xe2x80x9cModeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimationxe2x80x9d (Proc. IEEE International Conference on Computer-Aided Design, 1989). Therefore, a detailed description of the approximation method is omitted. In brief, the calculation of an admittance Y(S) is started from a downstream point according to a source pattern, the admittance Y(S) seen from the output of a source gate is calculated (refer to FIG. 3, an equation (19) and equations following the equation (19) in the literature), and a resistor R and capacitances C1 and C2 are determined (refer to equations (14) to (16) in the literature). Returning to the group of FIG. 5, FIG. 6 and FIG. 7, the source model 106 is connected with the load model 109, a response analysis is performed for the load model 109 shown in FIG. 7, and a delay time in the load model 109 is determined. The source model 106 is formed of the electric power source 104 and the resistor 105, and the source model 106 has a power source value and a resistance value according to a PMOS operation/an NMOS operation (an output is xe2x80x9cRisexe2x80x9d or xe2x80x9cFallxe2x80x9d) and an NMOS transistor actually operated among NMOS transistors arranged in series.
Next, an operation is described. For example, as shown in FIG. 8, the NAND circuit 101 having the two inputs is composed of two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2. Cd1 and Cd2 respectively indicates a parasitic capacitance of the output pin Y of the NAND circuit 101. In this configuration of the source model 106, when an electric potential of an input terminal A of the NAND circuit 101 is changed from a low (L) level to a high (H) level (a case of xe2x80x9cRisexe2x80x9d in a direction from the input terminal A to the output terminal Y), the PMOS transistor P1 is set to an xe2x80x9coffxe2x80x9d condition, the PMOS transistor P2 is set to an xe2x80x9conxe2x80x9d condition, the NMOS transistor N1 is set to an xe2x80x9coffxe2x80x9d condition, and the NMOS transistor N2 is set to an xe2x80x9conxe2x80x9d condition.
Also, as shown in FIG. 9, when an electric potential of an input terminal B of the NAND circuit 101 is changed from the L level to the H level (a case of xe2x80x9cRisexe2x80x9d in a direction from the input terminal B to the output terminal Y), the PMOS transistor P1 is set to an xe2x80x9conxe2x80x9d condition, the PMOS transistor P2 is set to an xe2x80x9coffxe2x80x9d condition, the NMOS transistor N1 is set to an xe2x80x9conxe2x80x9d condition, and the NMOS transistor N2 is set to an xe2x80x9coffxe2x80x9d condition.
It is also sometimes the case that the electric potential of the input terminal A is changed from the H level to the L level (a case of xe2x80x9cFallxe2x80x9d in the direction from the input terminal A to the output terminal Y), and it is sometimes the case that the electric potential of the input terminal B is changed from the H level to the L level (a case of xe2x80x9cFallxe2x80x9d in the direction from the input terminal B to the output terminal Y). Therefore, there are four logical paths in the two-input NAND circuit 101 functioning as a logic circuit. In the prior art, a source model 106 corresponding to the condition of each logical path is connected with the load model 109, the response analysis is performed for the load model 109, and a delay time in the load model 109 is determined as a delay time in the load constituent element 8.
Because the conventional method of producing a load for a delay time calculation is performed as is described above, the parasitic capacitance Cd1, the parasitic capacitance Cd2 or a composite parasitic capacitance Cd1+Cd2 is seen from the output pin Y of the NAND circuit 101 according to each of the four logical paths. That is, a parasitic capacitance denoting a part of the load is determined in dependence on the electric potential of each input terminal A or B. Therefore, because only one value is allocated to the parasitic capacitance of the fixed load model 109 in the conventional method in which the source model 106 is connected with the fixed load model 109 for each logical path, errors in the delay analysis are increased because of the change of the parasitic capacitance with the logical path. In particular, in cases where an area of the wire 103 and a load based on a gate capacitance are small, errors in the delay analysis are further increased. Therefore, there is a problem that a delay time in the load constituent element 108 cannot be calculated with high accuracy.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional method of producing a load for a delay time calculation, a method of producing a load for a delay time calculation in which a parasitic capacitance changing for each logical path is precisely indicated while using the conventional analyzing method.
The object is achieved by the provision of a method of producing a load for calculating a delay time of a logic circuit having a PMOS transistor and an NMOS transistor, comprising the steps of separating a parasitic capacitance of an output pin of the logic circuit from a load model denoting a load constituent element, and adding the parasitic capacitance corresponding to each of a plurality of logical paths of the logic circuit to the load model in a delay time calculation for the load model.
Because the logic circuit has a PMOS transistor and an NMOS transistor, there are a plurality of logical paths of the logic circuit, and the parasitic capacitance changes with the logical path of the logic circuit. In the present invention, because the parasitic capacitance is separated from the load model, the parasitic capacitance corresponding to each logical path of the logic circuit can be easily set and added to the load model in the delay time calculation for the load model.
Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy. Also, because the parasitic capacitance is indicated by only a capacitor, a composite load of both the parasitic capacitance and a load of the load model is equivalent to a xcfx80 type load which is obtained by combining the parasitic capacitance and the load model, and a delay time in the composite load can be calculated in the same manner as the method in the prior art.
It is preferred that the parasitic capacitance of the output pin is indicated by a single capacitive element.
Therefore, the calculation of the delay time can be performed in the same manner as the method in the prior art.
It is preferred that the parasitic capacitance of the output pin is indicated by a plurality of capacitive-resistive elements.
Therefore, the parasitic capacitance can be modeled in more detail, and the calculation of the delay time can be performed with high precision.
This method may be performed by a computer. A recording medium is provided that stores a computer program allowing the computer to perform the method. Therefore, the method of producing a load for calculating a delay time can be easily used.